Your partner for silicon IP and embedded systems solutions and web development. We provide staff and solutions for your next hardware or software project.
Smartfox Data Solutions Inc. is a silicon IP and design services provider based in Metro Manila, Philippines and founded by experienced IC and embedded systems design engineers. We are committed to enabling our customers get the most out of FPGA and ASIC enabled solutions for their data acquisition, processing, and storage demands.
Services
Digital Design
We offer digital IC design services from RTL design, logic synthesis and timing analysis to physical implementation. We specialize in design of co-processors, memory and storage controllers, and algorithmic cores.
Digital Verification
We have completed several verification projects using popular EDA softwares and industry proven methodologies such as Universal Verification Methodology (UVM), assertion-driven verification (SVAs), and coverage-driven verification.
FPGA and Embedded Systems
We perform HDL-level design, timing closure and optimization for designs targeted for implementation in popular FPGA platforms. We also develop custom software or firmware along with PCB and enclosure design.
Web Development and Software Testing
We provide front-end and back-end software development services for web applications. We also offer testing and QA services using latest agile testing methodologies.
Silicon IPs
We offer proven IP designs that can be easily integrated to your ASIC or FPGA project at competitive costs
AES Encoder/Decoder
- Implements reference design specified in NIST FIPS 197
- Supports 5 different block cipher modes
- Supports 128, 192 and 256-bit key widths
- 128-bit data input
- Encrypt and Decrypt both supported and can be done in parallel
JPEG Encoder
- Input matrix supported stream format YCbCr 4:4:4
- 8 bits input and output bitstream
- Fixed quantization table and compression level
- Single-stage header module
- Scan encoder performs Discrete cosine transform, Quantization, Run-length encoding
SHA2
- Reference design from FIPS 180-4 Secure Hash Standard
- Supported block sizes 512- and 1024-bit (SHA2-256 and SHA2-512 respectively)
- Message digest sizes supported are 256- and 512-bit
BCH Encoder/Decoder
- BCH encoder use linear-feedback shift register (LFSR) computation
- BCH decoder with reduced logic
- Block size from 8- to -256-bit
- Encode and Decode both supported
JPEG Decoder
- 8 bits input and output bitstream
- Output data format is YCbCr 4:4:4
- Decoder performs Run-length decoding, Dequantization, Inverse Discrete cosine transform
SHA3
- Reference design from FIPS 202 Permutation-based Hash and Extendable-output Functions
- Support input block is flexible and up to 1600-bit
- Message digest size supported is 256-bit
Partners and Clients
We Are SmartFox
We’re passionate about chip design, embedded systems, and related technologies.
3/F U.P. National Engineering Center
Agoncillo St. corner Osmena Ave.
University of the Philippines,
Diliman, Quezon City
Philippines 1101
+632 8981 8500 ext 8769
© Copyright SmartFox Data Solutions, Inc. 2024
